Certain electrical characteristics of modern digital circuitry (e.g., a serializer/deserializer (SerDes)) are often susceptible to variations in manufacturing process, power supply voltage and/or temperature (hereinafter referred to as “PVT”) conditions to which the circuitry may be subjected in a given application. Electrical characteristics which may be affected by such variations in PVT conditions include, but are not limited to, set-up and hold times, voltage drop (also referred to as current×resistance (IR) drop), delay, etc. Tight control over one or more of these electrical characteristics may be required in order to meet certain performance specifications for a given application of the circuitry.
In order to operate reliably over a specified PVT range, digital circuitry is conventionally designed for a worst-case (e.g., slowest) combination of PVT conditions. This approach, however, will typically yield a circuit which is over designed, and therefore too robust, for more favorable conditions under which the circuit will nominally operate. When process, power supply voltage and/or temperature deviate from worst-case conditions for which the circuit is designed to operate, the over designed circuit will undesirably consume significantly more power than is otherwise necessary for reliable operation of the circuit under those more favorable conditions. Additionally, a circuit designed for worst-case PVT conditions generally possesses a larger gate count than is otherwise necessary for reliable operation under more favorable conditions. This larger gate count results in a larger integrated circuit (IC) which is more costly to fabricate.
It is known to employ fuse programming and laser trimming in a wafer testing procedure (e.g., pre-packaging) in order to compensate the digital circuitry for delay variations due primarily to IC processing. However, this approach significantly increases IC testing time and, moreover, does not provide an adequate means of compensating the circuitry for variations in supply voltage and/or temperature.
Accordingly, there exists a need for techniques which would enable digital circuitry to operate reliably within a specified PVT range with reduced power consumption, and that does not suffer from one or more of the problems exhibited by conventional circuit design approaches.